Device and method of low voltage SCR protection for high voltage failsafe ESD applications

ABSTRACT

A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

FIELD OF THE INVENTION

[0001] The present invention is related in general to the field ofelectronic systems and semiconductor devices and more specifically to astructure and method of low voltage silicon controlled rectifier forpreventing destructive electrostatic discharge in high voltage failsafeapplications.

DESCRIPTION OF THE RELATED ART

[0002] Integrated circuits (ICs) may be severely damaged byelectrostatic discharge (ESD) events. A major source of ESD exposure toICs is from the charged human body (“Human Body Model”, HBM); thedischarge of the human body generates peak currents of several amperesto the IC for about 100 ns. A second source of ESD is from metallicobjects (“machine model”, MM); it can generate transients withsignificantly higher rise times than the HBM ESD source. A third sourceis described by the “charged device model” (CDM), in which the IC itselfbecomes charged and discharges to ground in the opposite direction thanshe HBM and MM ESD sources. More detail on ESD phenomena and approachesfor protection in ICs can be found in A. Amerasekera and C. Duvvury,“ESD in Silicon Integrated Circuits” (John Wiley & Sons LTD. London1995), and C. Duvvury, “ESD: Design for IC Chip Quality and Reliability”(Int. Symp. Quality in E1. Designs, 2000, pp. 251-259; references ofrecent literature).

[0003] ESD phenomena in ICs are growing in importance as the demand forhigher operating speed, smaller operating voltages, higher packingdensity and reduced cost drives a reduction of all device dimensions.This generally implies thinner dielectric layers, higher doping levelswith more abrupt doping transitions, and-higher electric fields—allfactors that contribute to an increased sensitivity to damaging ESDevents.

[0004] The most common protection schemes used inmetal-oxide-semiconductor (MOS) ICs rely on the parasitic bipolartransistor associated with an nMOS device whose drain is connected tothe pin to be protected and whose source is tied to ground. Theprotection level or failure threshold can be set by varying the nMOSdevice width from the drain to the source under the gate oxide of thenMOS device. Under stress conditions, the dominant current conductionpath between the protected pin and ground involves the parasitic bipolartransistor of that nMOS device. This parasitic bipolar transistoroperates in the snapback region under pin positive with respect toground stress events.

[0005] The dominant failure mechanism, found in the nMOS protectiondevice operating as a parasitic bipolar transistor in snapbackconditions, is the onset of second breakdown. Second breakdown is aphenomenon that induces thermal runaway in the device wherever thereduction of the impact ionization current is offset by the thermalgeneration of carriers. Second breakdown is initiated in a device understress as a result of self-heating. The peak nMOS device temperature, atwhich second breakdown is initiated, is known to increase with thestress current level.

[0006] In U.S. Pat. No. 4,939,616, issued on Jul. 3, 1990 (Rountree,“Circuit Structure with Enhanced Electrostatic Discharge Protection”), asilicon controlled rectifier (SCR) is described as a protection deviceagainst ESD wherein the trigger mechanism is avalanche conduction at theinterface between the n-well surrounding a portion of the protectiondevice and the p-type substrate. The lowered threshold voltage isprovided by a highly doped region of the same conductivity type as thewell at the interface between the well and the substrate. This highlydoped region is connected to a resistor which is then connected to theprotected node. The resistor and heavily doped region at theintersection between the n-well and substrate provide an additionalsource of current for avalanching at a lower voltage. Thus the triggervoltage of the protection system is substantially lowered. For today'sminiaturized circuit elements, however, the SCRs of the quoted patentare not fast enough and the described protection, therefore, notefficient enough.

[0007] In U.S. Pat. No. 5,903,032, issued on May 11, 1999 (Duvvury,“Power Device Integration for Built-in ESD Robustness”), covers thebasic concept of a drain-extended (DE) nMOS transistor integrated withan SCR. However, the patent does not describe the technique forsilicided technologies with lightly doped drain junctions—a structureand process commonly employed today. The patent is not sufficient fortoday's advanced CMOS technologies, which include shallow trenchisolation, low resistance substrates, and silicided diffusions, all ofwhich would essentially degrade the bipolar gains of the pnp and the npntransistors.

[0008] An urgent need has, therefore, arisen for a coherent, low-costmethod of enhancing ESD insensitivity without the need for additional,real-estate consuming protection devices. The device structures shouldfurther provide excellent electrical performance, mechanical stabilityand high reliability. The fabrication method should be simple, yetflexible enough for different semiconductor product families and a widespectrum of design and process variations. Preferably, these innovationsshould be accomplished without extending production cycle time, andusing the installed equipment, so that no investment in newmanufacturing machines is needed.

SUMMARY OF THE INVENTION

[0009] A semiconductor circuit for multi-voltage operation havingbuilt-in electrostatic discharge (ESD) protection is described,comprising a drain extended nMOS transistor and a pnpn siliconcontrolled rectifier (SCR) merged with the transistor so that a dual npnstructure is created and both the source of the transistor and thecathode of the SCR are connected to electrical ground potential, forminga dual cathode, whereby the ESD protection is enhanced. The rectifierhas a diffusion region, forming an abrupt junction, resistively coupledto the drain, whereby the electrical breakdown-to-substrate of the SCRcan be triggered prior to the breakdown of the nMOS transistor drain.The SCR has anode and cathode regions spaced apart by semiconductorsurface regions and insulating layers positioned over the surfaceregions with a thickness suitable for high voltage operation and ESDprotection.

[0010] For improved ESD protection, the invention uses a transistor withhigh breakdown voltage and complements it with a low voltage SCR thathas a low and fast trigger voltage. The low and fast trigger voltage isaccomplished by creating high gain npn and pnp parasitic transistorsusing a fabrication method characterized by two features:

[0011] blocking the lightly doped drain implant over the area of theSTI-blocked SCR. The invention provides a selective process by opening awindow in a photoresist layer so that a low energy, low dose ion implantcreates shallow, lightly doped layers under the surface only in regionsfor the extended source and drain of the MOS transistor; and

[0012] selecting localized silicon nitride walls in a thicknesssufficient to block the medium energy ion implant required for creatingthe deep source and drain regions.

[0013] In another embodiment of the invention, the process steps arereversed: The source drain implant is performed first and the siliconnitride walls are applied subsequently.

[0014] The device structure of the invention can be manufactured by twodistinctly different process flows:

[0015] Self-aligned STI-blocked SCR: The silicide blocking process step,actualized by patterned silicon nitride layers over the bases of the pnpand npn portions of the SCR, occurs before the source/drain implants. Inthis process, the silicon nitride is thick enough to preventsource/drain implant as well as silicide formation.

[0016] Non-aligned STI-blocked SCR: First, the SCR bases are defined bythe n+ and p+ source/drain (S/D) implants. Second, a layer of siliconnitride or silicon dioxide is patterned to protect the SCR except forfractional surface portions of the SCR anode and cathode. Third, theseunprotected portions are silicided.

[0017] In both process variations, silicide formation is prevented overthe bases of the bipolar elements (pnp and npn transistors).Consequently, electrical shorts between the bases and theircorresponding emitters/ collectors are prevented.

[0018] It is an aspect of the invention to merge an SCR and a MOStransistor by forming only a single well of a conductivity type oppositeto the conductivity type of the tank in which the well is embedded. Inthe example of a p-tank, the well is an n-well and the SCR is pnpn.

[0019] Another aspect of the invention is to increase ESD protection bya dual npn structure in the SCR, firstly p-diffusion /n-well/p-tank, andsecondly p-diffusion/n-diffusion /p-tank. This dual structure is enabledby the aspect of the invention to use a thick silicon nitride layer asprotection of the semiconductor surface regions (base of SCR) frommedium-energy n-type ion implantation, thus allowing efficient currentflow from p-diffusion to n-diffusion through lightly doped semiconductormaterial.

[0020] Another aspect of the invention is to leave this thick siliconnitride on the SCR for suppressing the silicide formation at thejunctions, which would not allow the SCR to trigger before reaching thefailure point of the built-in nMOS npn. Taking advantage of the lowerbreakdown voltage of the junctions initiates the SCR trigger before theavalanche of the high voltage transistor.

[0021] Another aspect of the invention is to provide ESD protection forhigh voltage failsafe applications without bias current and sufficientlylow and fast trigger voltage (failsafe I/O circuits are circuits on thebond pad that have no path for dc current regardless whether the deviceis powered “on” or “off”).

[0022] Another aspect of the invention is to require fewer ESD resistorsfor ESD protection than conventional protection circuits. This is anadvantage because ESD resistors increase driver size and outputcapacitance.

[0023] Another aspect of the invention is to provide protectioncompatible with the high voltage transistor junction by integrating theSCR into the device structure of the high voltage transistor structureand designing for a lower breakdown of the SCR.

[0024] Another aspect of the invention is to maximize the ESD protectionby reducing the shallow trench isolation width spacing the drain of theMOS transistor and the anode of the SCR to zero.

[0025] The invention applies to semiconductors both of p-type and n-typeas “first”, conductivity types. The invention is equally applicable tonMOS and pMOS transistors; the conductivity types of the semiconductorand the ion implant types are simply reversed.

[0026] The technical advances represented by the invention, as well asthe aspects thereof, will become apparent from the following descriptionof the preferred embodiments of the invention, when considered inconjunction with the accompanying drawings and the novel features setforth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027]FIG. 1 is a simplified cross section, together with a schematiccircuit diagram, of the STI-blocked silicon controlled rectifier mergedwith the drain expanded MOS transistor according to the first processembodiment of the present invention.

[0028]FIG. 2 is a simplified cross section, together with a schematiccircuit diagram, of the STI-blocked silicon controlled rectifier mergedwith the drain expanded MOS transistor according to the second processembodiment of the present invention.

[0029]FIG. 3 shows several structural device dimensions investigated inorder to optimize the ESD impact of the invention.

[0030]FIG. 4 (FIGS. 4A to 4D) depicts the schematic circuit diagrams ofthe arrangements from which the I-V characteristics of FIG. 3 aremeasured.

[0031]FIG. 5 compares the I-V characteristic of a device having thebenefit of the invention with I-V characteristics of devices without thebenefit of the invention.

[0032] FIGS. 6 to 16 are schematic and simplified cross sections of thesemiconductor surface portion illustrating individual process steps inthe fabrication flow of the ESD protection circuit according to theinvention.

[0033] FIGS. 10 to 12 are individual process steps applicable tofabricate the first embodiment of the invention; FIGS. 13 to 16 are notapplicable for the first embodiment.

[0034] FIGS. 13 to 16 are individual process steps applicable tofabricate the second embodiment of the invention; FIGS. 10 to 12 are notapplicable for the second embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] Failsafe I/O circuits are traditionally defined as circuits onthe bond pad that have no path for dc current regardless whether thedevice is powered “on” or “off”. To create ESD protection under failsafecircuit condition is particularly important for multi-voltage systemsthat vary I/O operating voltage in order to conserve power.

[0036] An additional concern the I/O's should meet for their ESDprotection is the amount of output capacitance seen at the bond pad.Since output capacitance restricts the overall bandwidth for bussolutions, I/O interfaces tend to be restrictive on allowable outputcapacitance. Providing solutions that have less capacitive loading willprovide a more successful circuit design.

[0037] Another obvious concern is chip real estate area. Althoughtolerance to higher voltage is gained, drain-extended transistors tendto have lower I-drive compared to their standard transistorcounterparts. This implies a disadvantage in the form of chip realestate. Area reduction needs to be leveraged off the intrinsicproperties of the drain-extended devices themselves.

[0038] For ESD phenomena in drain-extended transistors, the use of ann-well under the drain in nMOS devices allows higher voltage tolerance,but this advantage is off-set by an inefficient lateral npn turn-on withhigh holding voltage. Consequently, the device ESD performance is poorbecause of the high power dissipation. Previously proposed improvementsinclude the integration of an SCR (U.S. Pat. No. 5,903,032, issued May11, 1999, Duvvury, “Power Device Integration for Built-in ESDRobustness”), the application of the gate coupling effect (C. Duvvury etal., “Efficient npn Operation in High Voltage nMOSFET for ESDRobustness”, IEDM Digest, 1995), and an n+/p+ design (U.S. Pat. No.4,939,616, issued Jul. 3, 1990, Rountree, “Circuit Structure withEnhanced Electrostatic Discharge Protection”). These improvements havebecome more challenging with the recent technical advances of shallowtrench isolation (STI), low resistance substrate, and silicideddiffusions.

[0039] It is of particular interest for the current CMOS technologies,to optimize ESD protection structures by selecting circuit andgeometrical designs, such as spacings, to obtain the desired triggervoltage, allow high-voltage circuit operation, and provide ESDrobustness. SCR design optimization can thus influence HBM performance.

[0040] While the starting material for the device embodiments of theinvention is preferably silicon, it may also be silicon germanium,gallium arsenide, or any other semiconductor material used in integratedcircuit fabrication.

[0041]FIG. 1 shows a simplified cross section together with a schematiccircuit diagram of the first preferred embodiment, generally designated100, of the present invention. In the example of FIG. 1, theconductivity of the semiconductor substrate 101 is p-type. It should bestressed, however, that all considerations remain valid for the oppositeconductivity; consequently, the semiconductor substrate could be n-type.The p-doping species are selected from a group consisting of boron,aluminum, gallium, and indium. The n-doping species are selected fromarsenic, phosphorus, antimony, and bismuth.

[0042] A non-conductive isolation region 102, inserted in the p-typesemiconductor as a shallow trench isolation STI, defines the lateralboundaries of the active areas of the silicon controlled rectifier (SCR)103 and the drain extended MOS (DE-MOS) transistor 104. The width of theSTI region 102 is selected from a value between 0.6 and 0.2 μm, or zeroμm. The first embodiment 100 is characterized by the process flow(discussed, below) providing a “self-aligned STI-blocked SCR” (SBSCR).

[0043] Into the surface of the p-type semiconductor has been fabricateda p-tank 106; its resistivity range is about 1 to 50 Ω cm. Nested inthis p-tank is an n-well 107. This nested configuration of the n-wellcreates side walls 107 a and 107 b with the p-tank. Side wall 107 a,located in the device portion of the MOS transistor intersects thesurface at line 170 c. Side wall 107 d, located in the device portion ofthe SCR intersects one n+ diffusion of the npn transistor of the SCR atline 107 d.

[0044] Referring further to the embodiment of FIG. 1 and its choice ofconductivity types, the n+ drain region 108 of the MOS transistor, islocated in the n-well 107. The n+ source region 109 is located in p-tank106 and separated from the n-well 107 by a channel region 110 in thep-tank 106. Extending over channel region 110 is transistor gate 111,made of poly-silicon or other conductive material. Gate 111 is separatedfrom channel region 110 by insulating material 112, which is suitable asgate dielectric; a preferred material is silicon dioxide. Gate 111 has anarrow dimension from about 0.2 to 1.0 μm. The thickness of gate oxide112 is preferably between 2 and 10 nm. Gate 111 is surrounded byprotecting insulating material 113 such as silicon nitride. Gate 111 iselectrically connected to source 109 and ground potential. The lightlyn-doped drain 114 extends from source 109 towards gate 111.

[0045] The ground potential of source region 109 provides a secondarycathode. This feature improves the ESD protection efficiency of thedevice 100.

[0046] As FIG. 1 shows, the SCR 103 is merged with the drain extendedMOS transistor 104 into p-tank region 106 and a second portion of then-well 107. The p+ anode 115 of the SCR is fully located in the n-well107. Anode 115 is geometrically spaced from drain 108 by the trenchisolation 102, but is electrically connected to the drain. The n+cathode region is located in the p-tank; it is electrically connected toground potential. The other n+ region 117 of the npn transistor of theSCR is positioned between the anode 115 and cathode 116 such that oneportion of region 117 is located in p-tank 106, creating an abruptjunction, and the other portion is located in n-well 107. (As statedabove, side wall 107 b of the n-well intersects diffusion region 117 atline 107 d). Based on this arrangement, region 117 is resistivelycoupled by the n-well 107 to the drain 108 of the MOS transistor.Electrically, region 11-is referred to as a “floating” region.

[0047] Due to the abrupt junction of floating region 117, the “triggerdiffusion”, with p-tank 106, this region is configured to provide anelectrical breakdown of region 11-to p-tank 106 as the trigger mechanismof the SCR 103. The trigger mechanism is achieved prior to the breakdownof the drain 108 of the MOS transistor. This trigger of the SCR providesan ESD protection tolerant for high voltage operation while consumingminimum device area and avoiding any risk of gate oxide damage.

[0048] In the embodiment of FIG. 1, the spacing region between anode 115and diffusion region 117 has insulating material 118 on its surface,made of the same material as gate insulator 112. Likewise, the spacingregion between diffusion region 117 and cathode 116 has insulatingmaterial 119 on its surface. Over both insulating materials 118 and 119are insulating layers, designated 120 and 121 respectively. These layershave a thickness in the range from about 80 to 150 nm, and are selectedfrom a group consisting of silicon nitride, silicon dioxide, siliconoxynitride, polyimide, and stacked layers thereof. Layers 120 and 121are thus suitable for high voltage device operation, and capable toprotect the spacing regions underneath from medium energy p-type ionimplantation.

[0049] In terms of geometry, the channel length of channel region 110 ofthe drain extended MOS transistor 104 is greater than the semiconductorspacings between floating region 117 and anode 115, and floating region117 and cathode 116 of SCR 103.

[0050] As FIG. 1 shows, source 109, drain 108, anode 115, floatingregion 117, and cathode 116 have silicided surfaces 109 a, 108 a, 115 a,117 a, and 116 a, respectively.

[0051]FIG. 2 shows a simplified cross section together with a schematiccircuit diagram of the second preferred embodiment, generally designated200, of the present invention. The second embodiment 200 ischaracterized by the process flow (discussed below) providing a“non-aligned STI-blocked SCR” 203. In the example of FIG. 2, theconductivity of the semiconductor substrate 201 is p-type. It should bestressed, however, that all considerations remain valid for the oppositeconductivity; consequently, the semiconductor substrate could be n-type.

[0052] The design and material features of the p-tank 206, the n-well207, and the drain extended MOS transistor 204 are analogous to therespective features discussed in FIG. 1. The STI-blocked SCR 203,however, shows significant differences. The dielectric material 220,including silicon nitride or silicon dioxide, overlays the whole surfaceof the SCR except for a fractional surface portion 215 b of anode 215and a fractional surface portion 216 b of cathode 216. These fractionalsurface portions are silicided (215 a and 216 a, respectively). Theprocess flow required for the structure of FIG. 2 is described below.

[0053] The electrical connections of the structure depicted in FIG. 2are the same as the connections in FIG. 1. Consequently, the silicidedsurface fraction 215 b of anode 215 is connected to the drain 208 of thedrain extended MOS transistor 204, and the silicided surface fraction216 b of cathode 216 is connected to ground, as is the source 209 oftransistor 204.

[0054] The first embodiment of the present invention in FIG. 1, as wellas the second embodiment in FIG. 2, achieve efficient SCR action foradvanced CMOS technologies by blocking the STI. In order to integratethis requirement with the low-voltage LDD/silicide process, nitridemasks in the SCR process are needed. For the first embodiment (FIG.1),the silicide block process step is performed before source/drain (S/D)implant. The silicon nitride of the silicide-block mask is thick enoughto prevent S/D implant as well as silicide formation. This featureallows the blocking of silicide and S/D implant to be “self-aligned”. Inthe absence of STI and STI-block, all diffusions in FIG. 1 aresilicided. Effective npn and pnp transistors, with sufficiently lowleakage currents, can be created without STI between the anode andcathode.

[0055] The second embodiment in FIG. 2 creates the same characteristicsas described above by performing the S/D implant before the silicideblack process step employing an additional process step (see below) anda modified silicon nitride (220 in FIG. 2).

[0056] The circuit layouts in FIGS. 1 and 2 illustrate the triggeringmechanism of the SCR. In addition, two geometrical variables d1 and d2are shown which are available for optimization in order to achieve bestelectrical performance. d1 relates to the width of the STI; d2 is thetotal anode-cathode spacing. These variables are depicted in more detailin FIG. 3 together with a number of other dimensions of SCR spacingsessential for ESD optimization. Parameters b, c, d, x relate to the SCRtrigger behavior, parameter d1 to the investigation of the dual SCRphenomenon due to the secondary cathode. The guidelines for selectingthe variable values and reveal their interdependencies are:

[0057] Vary spacing “x” to study effect on trigger voltage;

[0058] Vary spacing “d1” to quantify dual SCR effect;

[0059] Monitor leakage with self-aligned SB-SCR.

[0060] The Table of FIG. 3 lists an example of experimental results.ESD2 is the control device.

[0061] Referring to the Table in FIG. 3, it lists various combinationsof the geometrical parameters and the resulting trigger voltage andfailure current It2; the data were collected with 100 ns pulse system.ESD1 has the shortest dimension for x, and correspondingly the lowesttrigger voltage. ESD6 has the largest dimension for x, and the largestanode-to-cathode spacing; the beneficial effect on the trigger voltageis obvious. As the Table demonstrates, the dimension x controls thetrigger voltage since it determines the npn trigger. On the other hand,ESD3 shows the highest failure-current It2.

[0062] In order to illustrate the improved ESD performance due to theinvention, FIGS. 4 and 5 compare different architectural configurations(FIG. 4) and their resulting current/voltage device characteristics(FIG. 5, current measured in A, voltage measured in V) for I/Oprotection applications (200 ns pulse system.

[0063]FIG. 4 A; FIG. 5, curve 501: Stand-alone grounded gate DE-nMOS.Experimental: Gate 50 μm wide, Leff=0.64 μm. Result: The grounded gateDE-nMOS does not show any snapback. Low failure current.

[0064]FIG. 4 B; FIG. 5, curve 502: Large DE-nMOS/pMOS failsafe outputwith no SCR protection. Experimental: 333 μm wide DE-pMOS with blockedback-gate diode; 333 μm wide DE-nMOS with typical pre-drivers connectedto their gates. Result: The large DE output structure shows some initialnpn snapback because of the gate coupling effect. Low failure current.

[0065]FIG. 4 C; FIG. 5, curve 503: Result: Shows breakdown at about 8 V.The trigger of Stand-alone SB-SCR. Experimental: 50 μm wide. the SCRwith a moderate on-resistance and failure at a current level inproportion to the pulse is observed.

[0066]FIG. 4 D; FIG. 5, curve 504: Integrated SB-SCR with 50 μm groundedgate DE-nMOS with input (combination of FIGS. 4 A and 4 C).Experimental: 5 μm wide DE-nMOS pass-gate to internal gates. Result:Triggers at 8.5 V well before the DE-nMOS and thus protect the DE-nMOS.Improvement over curve 503 indicated by the lower on-resistance.

[0067] Combination of FIGS. 4 B and 4 C; FIG. 5, curve 505: IntegratedSB-SCR with 50 μm grounded gate DE-nMOS. Result: The combination of theintegrated SB-SCR with a failsafe output with blocked back-gate diodeshows an even greater ESD performance. The gate coupling of the largeDE-nMOS (333 μm wide) acting in parallel with the integrated SB-SCRshows improved failure current over the stand-alone device FIG. 4 C;FIG. 5, curve 503).

[0068] FIGS. 6 to 16 describe the process flow for fabricating a SCRmerged with a drain extended MOS device according to the invention. Theprocess flow is illustrated for two embodiments; FIGS. 6 to 9 apply toboth flows. However, FIGS. 10 to 12 are the continued flow for the firstembodiment of the invention, while FIGS. 13 to 16 apply to the secondembodiment. The process flows are described for p-type semiconductormaterial as starting material, pnpn SCR, and nMOS transistor. It shouldbe stressed, however, that an analogous process flow description holdsfor n-type starting material, npnp SCR and pMOS transistor, since theinvention applies to both p-type and n-type material as firstconductivity type. The p-type semiconductor has a peak dopingconcentration between 4·10E17 and 1·10E18 cm−3 after background dopingadjustment implant.

[0069]FIG. 6: Forming non-conductive isolation regions 602 into thesurface 601 a of p-type semiconductor 601 for defining the lateralboundaries of the active areas of the MOS transistor and the SCR;

[0070]FIG. 7: Implanting n-doping ions into the p-type semiconductor 601to form an n-well 701 having side walls 701 a and 701 b; implantingp-doping ions into said p-type semiconductor 601 surrounding said n-wellside walls to form a p-tank 702;

[0071]FIG. 8: Depositing over the surface 601 a a layer 801 ofinsulating material suitable as gate dielectric, thereby covering saidSCR and transistor areas; depositing a layer of poly-silicon or otherconductive material onto insulating layer 801; protecting a portion ofthe poly-silicon and etching the remainder thereof, thereby defining thegate area 802 of the transistor at the location 703 where the n-wellside wall 701 a intersects the surface 601 a;

[0072]FIG. 9: Depositing a first photoresist layer and opening a window901 therein, thereby exposing the surface of the p-tank area adjacentsaid poly-silicon gate 802; implanting, at low energy, low dose n-dopingions 902 into said exposed surface area, thereby creating shallow,lightly n-doped layers 903 under said surface; the energy of the ions issuitable for creating the junction at a depth between 10 and 50 nm, andthe peak concentration is from about 5·10E17 to 5·10E20 cm−3; removingthe first photoresist layer;

[0073]FIG. 10: Depositing a conformal layer of dielectric materialincluding silicon nitride or silicon dioxide over the surface; forming asecond patterned photoresist layer to protect portions of the dielectriclayer defining the bases 1001 and 1002 of the pnp and the npn portionsof the SCR; directional plasma etching the dielectric layer so that theonly remaining dielectric forms side walls 1003 a and 1003 b around thepoly-silicon gate 802 and covers the extent of the base space chargeregions of the transistor; removing said second photoresist layer;

[0074]FIG. 11: Forming a third patterned photoresist layer to protect aportion of the surface defining the anode of the SCR; implanting, atmedium energy, n-doping ions into the surface, thereby creating n-dopedregions that extend to a medium depth under the surface, suitable asdeep source (1101 in FIG. 11) and drain (1102) of the transistor and asnpn portions (1103 and 1104) of the SCR; the energy of the ions issuitable for creating the junction at a depth between 50 and 200 nm, andthe peak concentration is from about 5·10E19 to 5·10E20 cm−3; removingsaid third photoresist layer; depositing a fourth photoresist layer andopening a window therein, thereby exposing the surface of the anode ofthe pnp portion of the SCR; implanting, at medium energy and high dose,p-doping ions into the window, thereby creating a p-doped region (1105in FIG. 11) at medium depth, suitable as anode of the SCR; the energy ofthe ions is suitable for creating the junction at a depth between 50 and200 nm, and the peak concentration is from about 5·10E19 to 5·10E20cm−3; removing the fourth photoresist layer;

[0075]FIG. 12: Removing the exposed gate dielectric; and siliciding thefreshly etched surfaces (1201 in FIG. 12, 1202, 1203, 1204, and 1205),thereby forming silicides only on the medium doped silicon regions.

[0076] The process flow for the second embodiment of the inventionstarts in FIG. 6, continues through FIG. 9, and then continues fromFIGS. 13 through 16.

[0077]FIG. 13: Depositing a first conformal layer of dielectric materialincluding silicon nitride or silicon dioxide over the surface;directional plasma etching the first dielectric layer so that the onlyremaining dielectric forms side walls 1303 a and 1303 b around thepoly-silicon gate 802 and covers the extent of the base space chargeregions of the transistor;

[0078]FIG. 14: Forming a second patterned photoresist layer to protect aportion of the surface, defining the anode of the SCR; implanting, atmedium energy, n-doping ions into the surface, thereby creating n-dopedregions that extend to a medium depth under the surface, suitable asdeep source 1401 and drain 1402 of the transistor and the npn portions1403 and 1404 of the SCR; the energy of the ions is suitable forcreating the junction at a depth between 50 and 200 nm, and the peakconcentration is from about 5·10E19 to 5·10E20 cm−3; removing the secondphotoresist layer; depositing a third photoresist layer and opening awindow therein, thereby exposing the surface of the anode of the pnpportion of the SCR; implanting, at medium energy and high dose, p-dopingions into the window, thereby creating a p-doped region 1405 at mediumdepth, suitable as-anode of the SCR; the energy of the ions is suitablefor creating the junction at a depth between 50 and 200 nm, and the peakconcentration is from about 5·10E19 to 5·10E20 cm−3; removing said thephotoresist layer;

[0079]FIG. 15: Depositing a second conformal layer of dielectricmaterial including silicon nitride or silicon dioxide over the surface;forming a fourth patterned photoresist layer to protect a portion of thesecond dielectric layer defining the SCR except for fractional surfaceportions of the anode and cathode; removing the second dielectric layerexcept for the photoresist-protected portion 1501, referred to as“silicide block mask”; removing the fourth photoresist layer; and

[0080]FIG. 16: Siliciding the freshly etched surfaces 1601, 1602, 1603,and 1604, including the fractional anode and cathode surface portions(1603 and 1604 respectively), thereby leaving the dielectric-protectedsurface areas of the SCR (areas under layer 1501) silicide-blocked.

[0081] For fabricating a pMOS transistor according to the method of thepresent invention, the flow of the above process steps applies inanalogous fashion with a reversal of conductivity types.

[0082] While this invention has been described in reference toillustrative embodiments, this description is not intended to beconstrued in a limiting sense. Various modifications and combinations ofthe illustrative embodiments, as well as other embodiments of theinvention, will be apparent to persons skilled in the art upon referenceto the description. It is therefore intended that the appended claimsencompass any such modifications or embodiments.

We claim:
 1. A semiconductor circuit for multi-voltage operation havingbuilt-in electrostatic discharge (ESD) protection comprising: a drainextended nMOS transistor; a pnpn silicon controlled rectifier mergedwith said nMOS transistor so that a dual npn structure is created andboth the source of said transistor and the cathode of said rectifier areconnected to electrical ground potential, forming a dual cathode,whereby the ESD protection is enhanced; said rectifier having adiffusion region, forming an abrupt junction, resistively coupled tosaid drain, whereby the electrical breakdown-to-substrate of saidrectifier can be triggered prior to the breakdown of said transistordrain; said rectifier having anode and cathode regions spaced apart bysemiconductor surface regions; and insulating layers positioned oversaid surface regions, said layers having a thickness suitable for highvoltage operation and ESD protection.
 2. The circuit according to claim1 wherein said drain of said transistor and said anode of said rectifierare spaced apart by an isolation region having a width from about 0.6 to0.2 μm.
 3. The circuit according to claim 2 wherein said isolationregion has a vanishing width.
 4. A semiconductor circuit formulti-voltage operation having built-in ESD protection comprising: adrain extended MOS transistor located in a tank region of a firstconductivity type, said drain extended MOS transistor including: a firstportion of a well region of a second conductivity type opposite saidfirst conductivity type located in said tank; a drain region of saidsecond conductivity type located in said well region; a source region ofsaid second conductivity type located in said tank and separated fromsaid well region by a channel region in said tank; a gate extending oversaid channel region, said gate having an electrical connection to saidsource and ground potential; and a silicon controlled rectifier mergedwith said drain extended MOS transistor into said tank region, saidsilicon controlled rectifier including: a second portion of said wellregion of said second conductivity type; an anode region of the firstconductivity type located in said well region, said anode region spacedfrom, but electrically connected to said drain region; a cathode regionof the second conductivity type located in said tank, said cathodeconnected to electrical ground potential; a diffusion region of thesecond conductivity type positioned between said anode and said cathodesuch that one portion of said diffusion region is located in said tankand the other portion in said well, whereby said diffusion region isresistively coupled by said well to said drain of said MOS transistor;insulator layers located over each semiconductor spacing region betweensaid anode, diffusion region, and cathode, said insulator layers havingthicknesses suitable for high voltage operation.
 5. The circuitaccording to claim 4 wherein said semiconductor material is selectedfrom a group consisting of silicon, silicon germanium, gallium arsenide,and any other semiconductor material used in integrated circuitfabrication.
 6. The circuit according to claim 4 wherein said tank ofthe first conductivity type is made of p-type silicon in the resistivityrange from about 1 to 50 ω cm, and said opposite conductivity type isn-type.
 7. The circuit according to claim 4 wherein said spacing betweensaid drain and said anode has a width selected from a value between 0.6and 0.2 μm or zero μm.
 8. The circuit according to claim 4 wherein saidinsulating layer has a thickness in the range from about 80 to 150 nmand is selected from a group consisting of silicon nitride, silicondioxide, silicon oxynitride, polyimide, and stacked layers thereof,whereby said semiconductor spacings under said insulating layers areprotected from medium energy p-type ion implantation.
 9. The circuitaccording to claim 4 wherein the regions of said first conductivity typehave a dopant species selected from a group consisting of boron,aluminum, gallium, and indium, while the regions of said secondconductivity type have a dopant species selected from a group consistingof arsenic, phosphorus, antimony, and bismuth.
 10. The circuit accordingto claim 4 wherein said gate has a narrow dimension from about 0.2 to1.0 μm.
 11. The circuit according to claim 4 wherein said source anddrain regions of said extended MOS transistor and said anode, cathodeand floating regions have silicided surfaces.
 12. The circuit accordingto claim 4 wherein said spacing between said anode and said drain is ashallow trench isolation.
 13. The circuit according to claim 4 whereinsaid portions of said floating region are configured to provide anelectrical breakdown of said region to said tank as the triggermechanism for said silicon controlled rectifier, whereby said triggermechanism is achieved prior to the breakdown of the drain of the MOStransistor.
 14. The circuit according to claim 13 wherein said triggerof said silicon controlled rectifier provides an ESD protection tolerantfor high voltage operation while consuming minimum device area andavoiding any risk of gate oxide damage.
 15. The circuit according toclaim 4 wherein said ground potential of said source region provides asecondary cathode, whereby the ESD protection efficiency is improved.16. The circuit according to claim 4 wherein a channel length of saiddrain extended MOS transistor is greater than said semiconductorspacings between said floating region and said anode, and said floatingregion and said cathode.
 17. A method of fabricating into the surface ofa n-well, having first and second side-walls in a p-tank, a pnpn SCRintegrated with a drain-extended nMOS transistor for multi-voltageoperation having built-in ESD protection, said surface having a layer ofinsulating material suitable as gate dielectric and a poly-silicon gatedeposited on said insulating layer at the location where said firstside-wall intersects said surface, comprising the steps of: depositing afirst photoresist layer and opening a window therein, thereby exposingthe surface of said p-tank area adjacent said poly-silicon gate andcovering said n-well and said p-tank adjacent said second side-wall;implanting, at low energy and low dose, n-doping ions into said exposedsurface area, thereby creating shallow, lightly n-doped layers undersaid surface and leaving the area under the photoresist unimplanted;removing said first photoresist layer; depositing a conformal layer ofdielectric material including silicon nitride or silicon dioxide oversaid surface; forming a second patterned photoresist layer to protectportions of said dielectric layer defining the bases of the pnp and thenpn portions of said SCR; directional plasma etching said dielectriclayer so that the only remaining dielectric forms side walls around saidpoly-silicon gate and covers the extent of the base space charge regionsof said transistor; removing said second photoresist layer; forming athird patterned photoresist layer to protect a portion of said surfacedefining the anode of said SCR; implanting, implanting, at mediumenergy, n-doping ions into said surface, thereby creating n-dopedregions that extend to a medium depth under said surface, suitable asdeep source and drain of said transistor and as npn portion of said SCR,the junction of one of said SCR n-regions partially formed with saidp-tank and partially with said n-well; removing said third photoresistlayer; depositing a fourth photoresist layer and opening a windowtherein, thereby exposing the surface of said anode of said pnp port-onof said SCR; implanting, at medium energy and high dose, p-doping ionsinto said window, thereby creating a p-doped region at medium depth,suitable as anode of said SCR; and removing said fourth photoresistlayer.
 18. A method of fabricating into the surface of a p-typesemiconductor a pnpn silicon controlled rectifier (SCR) integrated witha drain-extended nMOS transistor for multi-voltage operation havingbuilt-in ESD protection, comprising the steps of: forming non-conductiveisolation regions into said p-type semiconductor for defining thelateral boundaries of the active areas of said MOS transistor and saidSCR; implanting n-doping ions into said p-type semiconductor to form ann-well having side walls; implanting p-doping ions into said p-typesemiconductor surrounding said n-well side walls to form a p-tank;depositing over said surface a layer of insulating material suitable asgate dielectric, thereby covering said SCR and transistor areas;depositing a layer of poly-silicon or other conductive material ontosaid insulating layer; protecting a portion of said poly-silicon andetching the remainder thereof, thereby defining the gate area of saidtransistor at the location where said n-well side wall intersects saidsurface; depositing a first photoresist layer and opening a windowtherein, thereby exposing the surface of said p-tank area adjacent saidpoly-silicon gate; implanting, at low energy, low dose n-doping ionsinto said exposed surface area, thereby creating shallow, lightlyn-doped layers under said surface; removing said first photoresistlayer; depositing a conformal layer of dielectric material includingsilicon nitride or silicon dioxide over said surface; forming a secondpatterned photoresist layer to protect portions of said dielectric layerdefining the bases of the pnp and the npn portions of said SCR;directional plasma etching said dielectric layer so that the onlyremaining dielectric forms side walls around said poly-silicon gate andcovers the extent of the base space charge regions of said transistor;removing said second photoresist layer; forming a third patternedphotoresist layer to protect a portion of said surface defining theanode of said SCR; implanting, at medium energy, n-doping ions into saidsurface, thereby creating n-doped regions that extend to a medium depthunder said surface, suitable as deep source and drain of said transistorand as npn portions of said SCR; removing said third photoresist layer;depositing a fourth photoresist layer and opening a window therein,thereby exposing the surface of said anode of said pnp portion of saidSCR; implanting, at medium energy and high dose, p-doping ions into saidwindow, -hereby creating a p-doped region at medium depth, suitable asanode of said SCR; removing said fourth photoresist layer; and removingsaid exposed gate dielectric and siliciding the freshly etched surfaces,thereby forming silicides only on the medium doped silicon regions. 19.The method according to claim 18 wherein said step of formingnon-conductive isolation regions is modified by not forming saidisolation region between said drain of said transistor and said anode ofsaid rectifier.
 20. The method according to claim 18 wherein thethickness of said first photoresist layer is larger than a thicknesssolely required to block said low-energy ion implant.
 21. The methodaccording to claim 18 wherein said p-type semiconductor has a peakdoping concentration between 4·10E17 and 1·10E18 cm−3 after saidbackground doping adjustment implant.,
 22. The method according to claim18 wherein said implanting of low energy ions comprises ions having anenergy suitable for creating the junction at a depth between 10 and 50nm, and a peak concentration from about 5·10E17 to 5·10E20 cm−3.
 23. Themethod according to claim 18 wherein said implanting of medium energyions comprises ions having an energy suitable for creating the junctionat a depth between 50 and 200 nm, and a peak concentration from about5·10E19 to 5·10E20 cm−3.
 24. A method of fabricating into the surface ofa p-well, having first and second side-walls in a n-tank, a npnp SCRintegrated with a drain-extended pMOS transistor for multi-voltageoperation having built-in ESD protection, said surface having a layer ofinsulating material suitable as gate dielectric and a poly-silicon gatedeposited on said insulating layer at the location where said first sidewall intersects said surface, comprising the steps of: depositing afirst photoresist layer and opening a window therein, thereby exposingthe surface of said n-tank area adjacent said poly-silicon gate andcovering said p-well and said n-tank adjacent said second side-wall;implanting, at low energy and low dose, p-doping ions into said exposedsurface area, thereby creating shallow, lightly p-doped layers undersaid surface and leaving the area under the photoresist unimplanted;removing said first photoresist layer; depositing a conformal layer ofdielectric material including silicon nitride or silicon dioxide oversaid surface; forming a second patterned photoresist layer to protectportions of said dielectric layer defining the bases of the npn and pnpportions of said SCR; directional plasma etching said dielectric layerso that the only remaining dielectric forms side walls around saidpoly-silicon gate and covers the extent of the base space charge regionsof said transistor; removing said second photoresist layer; forming athird patterned photoresist layer to protect a portion of said surfacedefining the anode of said SCR; implanting, at medium energy, p-dopingions into said surface, thereby creating p-doped regions that extend toa medium depth under said surface, suitable as deep source and drain ofsaid transistor and as pnp portion of said SCR, the junction of one ofsaid SCR p-regions partially formed with said n-tank and partially withsaid p-well; removing said third photoresist layer; depositing a fourthphotoresist layer and opening a window therein, thereby exposing thesurface of said anode of said npn portion of said SCR; implanting, atmedium energy and high dose, n-doping ions into said window, therebycreating a n-doped region at medium depth, suitable as anode of saidSCR; and removing said fourth photoresist layer.
 25. A method offabricating into the surface of a n-type semiconductor a npnp SCRintegrated with a drain-extended pMOS transistor for multi-voltageoperation having built-in ESD protection, comprising the steps of:forming non-conductive isolation regions into said n-type semiconductorfor defining the lateral boundaries of the active areas of said MOStransistor and said SCR; implanting p-doping ions into said n-typesemiconductor to form an p-well having side walls; implanting n-dopingions into said n-type semiconductor surrounding said p-well side wallsto form a n-tank; depositing over said surface a layer of insulatingmaterial suitable as gate dielectric, thereby covering said SCR andtransistor areas; depositing a layer of poly-silicon or other conductivematerial onto said insulating layer; protecting a portion of saidpoly-silicon and etching the remainder thereof, thereby defining thegate area of said transistor at the location where said p-well side wallintersects said surface; depositing a first photoresist layer andopening a window therein, thereby exposing the surface of said n-tankarea adjacent said poly-silicon gate; implanting, at low energy, lowdose p-doping ions into said exposed surface area, thereby creatingshallow, lightly p-doped layers under said surface; removing said firstphotoresist layer; depositing a conformal layer of dielectric materialincluding silicon nitride or silicon dioxide over said surface; forminga second patterned ohotoresist layer to protect portions of saiddielectric layer defining the bases of the npn and pnp portions of saidSCR; directional plasma etching said insulating layer so that the onlyremaining dielectric forms side walls around said poly-silicon gate andcovers the extent of the base space charge regions of said transistor;removing said second photoresist layer; forming a third patternedphotoresist layer to protect a portion of said surface defining theanode of said SCR; implanting, at medium energy, p-doping ions into saidsurface, thereby creating p-doped regions that extend to a medium depthunder said surface, suitable as deep source and drain of said transistorand as pnp portions of said SCR; removing said third photoresist layer;depositing a fourth photoresist layer and opening a window therein,thereby exposing the surface of said cathode of said npn portion of saidSCR; implanting, at medium energy and high dose, n-doping ions into saidwindow, thereby creating a n-doped region at medium depth, suitable ascathode of said SCR; removing said fourth photoresist layer; andremoving said exposed gate dielectric; and siliciding the freshly etchedsurfaces, thereby forming silicides only on the medium doped siliconregions.
 26. The method according to claim 25 wherein said step offorming non-conductive isolation regions is modified by not forming saidisolation region between said drain of said transistor and said anode ofsaid rectifier.
 27. The method according to claim 25 wherein thethickness of said first photoresist layer is larger than a thicknesssolely required to block said low-energy ion implant.
 28. The methodaccording to claim 25 wherein said n-type semiconductor has a peakdoping concentration between 4·10E17 and 1·10E18 cm−3 after saidbackground doping adjustment implant.
 29. The method according to claim25 wherein said implanting of low energy ions comprises ions having anenergy suitable for creating the junction at a depth between 10 and 50nm, and a peak concentration from about 5·10E17 to 5·10E20 cm−3.
 30. Themethod according to claim 25 wherein said implanting of medium energyions comprises ions having an energy suitable for creating the junctionat a depth between 50 and 200 nm, and a peak concentration from about5·10E19 to 5·10E20 cm−3.
 31. A method of fabricating into the surface ofa n-well, having first and second side-walls in a p-tank, a pnpn SCRintegrated with a drain-extended nMOS transistor for multi-voltageoperation having built-in ESD protection, said surface having a layer ofinsulating material suitable as gate dielectric and a poly-silicon gatedeposited on said insulating layer at the location where said firstside-wall intersects said surface, comprising the steps of: depositing afirst phctoresist layer and opening a window therein, thereby exposingthe surface of said p-tank area adjacent said poly-silicon gate andcovering said n-well and said p-tank adjacent said second side-wall;implanting, at low energy and low dose, n-doping ions into said exposedsurface area, thereby creating shallow, lightly n-doped layers undersaid surface and leaving the area under the photoresist unimplanted;removing said first photoresist layer; depositing a first conformallayer of dielectric material including silicon nitride or silicondioxide over said surface; directional plasma etching said firstdielectric layer so that the only remaining dielectric forms side wallsaround said poly-silicon gate and covers the extent of the base spacecharge regions of said transistor; forming a second patternedphotoresist layer to protect a portion of said surface defining theanode of said SCR; implanting, at medium energy, n-doping ions into saidsurface, thereby creating n-doped regions that extend to a medium depthunder said surface, suitable as deep source and drain of said transistorand said npn portions of said SCR; removing said second photoresistlayer; depositing a third photoresist layer and opening a windowtherein, thereby exposing the surface of said anode of said pap portionof said SCR; implanting, at medium energy and high dose, p-doping ionsinto said window, thereby creating a p-doped region at medium depth,suitable as anode of said SCR; removing said third photoresist layer;depositing a second conformal layer of dielectric material includingsilicon nitride or silicon dioxide over said surface; forming a fourthpatterned photoresist layer to protect a portion of said conformal layerdefining said SCR except for fractional surface portions of said anodeand cathode; removing said second dielectric layer except for saidphotoresist-protected portion; removing said fourth photoresist layer;and siliciding the freshly etched surfaces, including said fractionalanode and cathode surface portions, thereby leaving thedielectric-protected surface areas of said SCR silicide-blocked.
 32. Amethod of fabricating into the surface of a p-type semiconductor a pnpnSCR integrated with a drain-extended nMOS transistor for multi-voltageoperation having built-in ESD protection, comprising the steps of:forming non-conductive isolation regions into said p-type semiconductorfor defining the lateral boundaries of the active areas of said MOStransistor and said SCR; implanting n-doping ions into said p-typesemiconductor to form a n-well having side walls; implanting p-dopingions into said p-type semiconductor surrounding said n-well side wallsto form a p-tank; depositing over said surface a layer of insulatingmaterial suitable as gate dielectric, thereby covering said SCR andtransistor areas; depositing a layer of poly-silicon or other conductivematerial onto said insulating layer; protecting a portion of saidpoly-silicon and etching the remainder thereof, thereby defining thegate area of said transistor at the location where said n-well side wallintersects said surface; depositing a first photoresist layer andopening a window therein, thereby exposing the surface of said p-tankarea adjacent said poly-silicon gate; implanting, at low energy, lowdose n-doping ions into said exposed surface area, thereby creatingshallow, lightly n-doped layers under said surface; removing said firstphotoresist layer; depositing a first conformal layer of dielectricmaterial including silicon nitride or silicon dioxide over said surface;directional plasma etching said first dielectric layer so that the onlyremaining dielectric forms side walls around said poly-silicon gate andcovers the extent of the base space charge regions of said transistor;forming a second patterned photoresist layer to protect a portion ofsaid surface, defining the anode of said SCR; implanting, at mediumenergy, n-doping ions into said surface, thereby creating n-dopedregions that extend to a medium depth under said surface, suitable asdeep source and drain of said transistor and said npn portion of saidSCR; removing said second photoresist layer; depositing a thirdphotoresist layer and opening a window therein, thereby exposing thesurface of said anode of said pnp portion of said SCR; implanting, atmedium energy and high dose, p-doping ions into said window, therebycreating a p-doped region at medium depth, suitable as anode of saidSCR; removing said third photoresist layer; depositing a secondconformal layer of dielectric material including silicon nitride orsilicon dioxide over said surface; forming a fourth patternedphotoresist layer to protect a portion of said second dielectric layerdefining said SCR except for fractional surface portions of said anodeand cathode; removing said second dielectric layer except for saidphotoresist-protected portion; removing said fourth photoresist layer;and siliciding the freshly etched surfaces, including said fractionalanode and cathode surface portions, thereby leaving thedielectric-protected surface areas of said SCR silicide-blocked.
 33. Amethod of fabricating into the surface of a p-well, having first andsecond side-walls in a n-tank, a npnp SCR integrated with adrain-extended pMOS transistor for multi-voltage operation havingbuilt-in ESD protection, said surface having a layer of insulatingmaterial suitable as gate dielectric and a poly-silicon gate depositedon said insulating layer at the location where said first side-wallintersects said surface, comprising the steps of: depositing a firstphotoresist layer and opening a window therein, thereby exposing thesurface of said n-tank area adjacent said poly-silicon gate and coveringsaid p-well and said n-tank adjacent said second side-wall; implanting,at low energy and low dose, p-doping ions into said exposed surfacearea, thereby creating shallow, lightly p-doped layers under saidsurface and leaving the area under the photoresist unimplanted; removingsaid first photoresist layer; depositing a first conformal layer ofdielectric material including silicon nitride or silicon dioxide oversaid surface; directional plasma etching said first dielectric layer sothat the only remaining dielectric forms side walls around saidpoly-silicon gate and covers the extent of the base space charge regionsof said transistor; forming a second patterned photoresist layer toprotect a portion of said surface defining the anode of said SCR;implanting, at medium energy, p-doping ions into said surface, therebycreating p-doped regions that extend to a medium depth under saidsurface, suitable as deep source and drain of said transistor and saidpnp portions of said SCR; removing said second photoresist layer;depositing a third photoresist layer and opening a window therein,thereby exposing the surface of said anode of said npn portion of saidSCR; implanting, at medium energy and high dose, n-doping ions into saidwindow, thereby creating a n-doped region at medium depth, suitable asanode of said SCR; removing said third photoresist layer; depositing asecond conformal layer of dielectric material including silicon nitrideor silicon dioxide over said surface; forming a fourth patternedphotoresist layer to protect a portion of said conformal layer definingsaid SCR except for fractional surface portions of said anode andcathode; removing said second dielectric layer except for saidphotoresist-protected portion; removing said fourth photoresist layer;and siliciding the freshly etched surfaces, including said fractionalanode and cathode surface portions, thereby leaving thedielectric-protected surface areas of said SCR silicide-blocked.
 34. Amethod of fabricating into the surface of a n-type semiconductor a npnpSCR integrated with a drain-extended nMOS transistor for multi-voltageoperation having built-in ESD protection, comprising the steps of:forming non-conductive isolation regions into said n-type semiconductorfor defining the lateral boundaries of the active areas of said MOStransistor and said SCR; implanting p-doping ions into said n-typesemiconductor to form a p-well having side walls; implanting n-dopingions into said n-type semiconductor surrounding said p-well side wallsto form a n-tank; depositing over said surface a layer of insulatingmaterial suitable as gate dielectric, thereby covering said SCR andtransistor areas; depositing a layer of poly-silicon or other conductivematerial onto said insulating layer; protecting a portion of saidpoly-silicon and etching the remainder thereof, thereby defining thegate area of said transistor at the location where said p-well side wallintersects said surface; depositing a first photoresist layer andopening a window therein, thereby exposing the surface of said n-tankarea adjacent said poly-silicon gate; implanting, at low energy, lowdose p-doping ions into said exposed surface area, thereby creatingshallow, lightly p-doped layers under said surface; removing said firstphotoresist layer; depositing a first conformal layer of dielectricmaterial including silicon nitride or silicon dioxide over said surface;directional plasma etching said first dielectric layer so that the onlyremaining dielectric forms side walls around said poly-silicon gate andcovers the extent of the base space charge regions of said transistor;forming a second patterned photoresist layer to protect a portion ofsaid surface, defining the anode of said SCR; implanting, at mediumenergy, p-doping ions into said surface, thereby creating p-dopedregions that extend to a medium depth under said surface, suitable asdeep source and drain of said transistor and said pnp portion of saidSCR; removing said second photoresist layer; depositing a thirdphotoresist layer and opening a window therein, thereby exposing thesurface of said anode of said npn portion of said SCR; implanting, atmedium energy and high dose, n-doping ions into said window, therebycreating a n-doped region at medium depth, suitable as anode of saidSCR; removing said third photoresist layer; depositing a secondconformal layer of dielectric material including silicon nitride orsilicon dioxide over said surface; forming a fourth patternedphotoresist layer to protect a portion of said second dielectric layerdefining said SCR except for fractional surface portions of said anodeand cathode; removing said second dielectric layer except for saidphotoresist-protected portion; removing said fourth photoresist layer;and siliciding the freshly etched surfaces, including said fractionalanode and cathode surface portions, thereby leaving thedielectric-protected surface areas of said SCR silicide-blocked.